1. Field of the Invention
The present invention relates to the making of interconnect solder bumps on a wafer or other electronic device without depositing any significant amount of tin from the solder onto the wafer surface which tin can cause shorts or other defects in the wafer, and, in particular, to the well-known C4NP interconnect technology.
2. Description of Related Art
Forming an electronic package assembly whereby an electrical component such as an integrated circuit chip is electrically and mechanically connected to a substrate, a card, or board, another chip or another electronic part is well-known in the art. This technology is generally termed surface mount technology (SMT) and has gained acceptance as the preferred means of making electronic package assemblies. The interconnect technology is commonly known as ball grid array packaging, C4 flip chip interconnect, multi-chip modules, multilayer and micro via printed wiring boards and surface mount hybrid assembly.
Multilayer ceramic and organic electronic components are typically joined to other components by soldering (or capture) pads on a surface of one of the electronic components to corresponding soldering (or capture) pads on the surface of the other component. Control Collapse Chip Connection is an interconnect technology developed by IBM as an alternative to wirebonding. This technology is generally known as C4 technology or flip chip packaging. Broadly stated, an integrated circuit chip is mounted above a ceramic or organic substrate and pads on the chip are electrically and mechanically connected to corresponding pads on the substrate by a plurality of electrical connections such as solder bumps to form an electronically connected module. A module is typically connected to other electronic components by solder or socket type connections.
In the C4 interconnect technology a relatively small solder bump is attached to the pads on one of the components being joined, typically to the chip. The electrical and mechanical interconnects are then formed by positioning the corresponding pads on the substrate to be joined adjacent the solder bumps on the chip and reflowing the bumps at an elevated temperature. The C4 joining process is self-aligning in that the wetting action of the solder will align the chip bump pattern to the corresponding pads on the substrate. Capture pads can also be sputtered and subsequently etched without any plating.
Capture pads for C4 bumps on semiconductor wafers or on the substrate to be interconnected are well-known and are typically made by a through resist plating of Ni or Cu/Ni pads onto a Cu seed layer. It is also preferred to use a conductive barrier layer on the substrate surface and the Cu seed layer is preferably made by sputtering of Cu onto a sputtered TiW layer.
In C4 technology the solder bumps are formed directly on the capture pads of the one unit. The pads are electrically isolated from other pads by the insulating chip passivation and substrate that surrounds each pad. The substrate may be un-doped silicon (Si) or some other material. The bottom of the pad is electrically connected into the chip or substrate circuit.
A major application of C4 is in joining semiconductor microchips (integrated circuits) to chip packages. Chips usually are made in rectangular arrays on a mono-crystalline slab of silicon called a “wafer,” which is a thin disc several inches across. Many chips are formed on each wafer, and then the wafer is diced into individual chips and the chips are “packaged” in units large enough to be handled. The C4 bumps are placed on the chips while they are still joined in a wafer.
One method of forming solder bumps uses sputtering or vacuum deposition. Solder metal is evaporated in a vacuum chamber and the metal vapor coats everything in the chamber with a thin film of the evaporated metal. To form solder bumps on the substrate, the vapor is allowed to pass through holes in a metal mask held over the substrate. The solder vapor passing through the holes condenses onto the cool surface into solder bumps. This method requires a high vacuum chamber to hold the substrate, mask, and flash evaporator.
An alternative technique for making solder bumps is electrodeposition, also called electrochemical plating or electroplating. This method also uses a mask such as patterned photoresist and forms solder bumps only at the selected sites. Other methods include screening a solder paste through a mask and depositing micro-bumps in place.
The C4NP transfer process is the preferred method and uses a mold containing the solder and transfers the solder in the mold to the capture pad of the wafer and upon heating forms solder bumps on the wafer pads. The process however may result in organo-Sn and Sn or other components of the solder being deposited on the surface of the wafer during transfer processing. These wafers will be rejected due to these surface deposits because the presence of these deposits is a source of high resistance shorts between C4's and paths for electro-migration fails during field use. The mold solder bumps are preferably filled with solder by an Injection Molding Solder (IMS) method as described below.
Bearing in mind the deficiencies of the prior art it is an object of the present invention to improve the C4NP process and in particular the method for the transfer of the solder in the mold to the capture pad of the wafer substrate.
Still other objects and advantages of the invention will in part be obvious and will in part be apparent from the specification.